dc C 12 ghz high efficiency gaas hbt mmic divide-by-8 prescaler technical data HMMC-3028 features ? wide frequency range: 0.2 - 12 ghz ? high input power sensitivity: on-chip pre- and post-amps -20 to +10 dbm (1 - 8 ghz) -15 to +10 dbm (8 - 10 ghz) -10 to +5 dbm (10 - 12 ghz) ? dual-mode p out : (chip form) -6.0 dbm [0.25 v p-p ] @ 34 ma 0 dbm [0.5 v p-p ] @ 44 ma ? low phase noise: -153 dbc/hz @ 100 khz offset ? (+) or (-) single supply bias operation ? wide bias supply range: 4.5 to 6.5 volt operating range ? differential i/0 with on-chip 50 w matching description the HMMC-3028 gaas hbt mmic prescaler offers dc to 12 ghz frequency translation for use in communications and ew systems incorporating high- frequency pll oscillator circuits and signal-path down conversion applications. the prescaler provides a large input power sensitivity window and low phase noise. in addition to the features listed above the device offers input disable and circuit power- down contact pads to eliminate any self-oscillation condition or reduced power consumption. chip size: 1330 x 440 m m (52.4 x 17.3 mils) chip size tolerance: 10 m m ( 0.4 mils) chip thickness: 127 15 m m (5.0 0.6 mils) pad dimensions: 70 x 70 m m (2.8 x 2.8 mils) absolute maximum ratings [1] (@ t a = 25 c, unless otherwise indicated) symbol parameters/conditions units min. max. v cc bias supply voltage volts +7 v ee bias supply voltage volts -7 |v cc - v ee | bias supply delta volts +7 v disable pre-amp disable voltage volts v ee v cc v pwrdwn prescaler power-down voltage volts v ee v cc v logic logic threshold voltage volts v cc -1.5 v cc -1.2 p in(cw) cw rf input power dbm +10 v rfin dc input voltage volts v cc 0.5 (@ rfin or rfin ports) t bs [2] backside operating temp c -40 +85 t stg storage temperature c -65 +165 t max maximum assembly temp c 310 (60 seconds max.) notes: 1. operation in excess of any parameter limit (except t bs ) may cause permanent damage to the device. 2. mttf > 1 x 10 6 hours @ t bs < 85 c. operation in excess of maximum operating temperature (t bs ) will degrade mttf.
2 dc specifications/physical properties [1] , (t a = 25 c, v cc - v ee = 5.0 v unless otherwise listed) symbol parameters and test conditions units min. typ. max. v cc - v ee operating bias supply difference [1] volts 4.5 5.0 6.5 bias supply current ma 37 44 51 |i cc | or |i ee | ( high output power configuration [2] : v pwrsel = v ee ) bias supply current ma 29 34 39 ( low output power configuration [2] : v pwrsel = open) v rfin(q) quiescent dc voltage appearing at all rf ports volts v cc v logic nominal ecl logic level volts v cc - 1.45 v cc - 1.32 v cc - 1.25 (v logic contact self-bias voltage, generated on-chip) i ee(off) residual bias supply current ma 5.5 (v pwrdwn = v cc ) notes: 1. prescaler will operate over full specified supply voltage range. v cc or v ee not to exceed limits specified in absolute maximum ratings section. 2. high output power configuration: p out = 0 dbm [v out = 0.5 v p-p ], low output power configuration: p out = -6.0 dbm [v out = 0.25 v p-p ]. HMMC-3028 ( ? 8) rf specifications, (t a = 25 c, z o = 50 w , v cc - v ee = 5.0 v) symbol parameters and test conditions units min. typ. max. | in(max) maximum input frequency of operation ghz 12 14 | in(min) minimum input frequency of operation [1] ghz 0.2 0.5 (p in = -10 dbm) | self-osc. output self-oscillation frequency [2] ghz 1.7 @ dc, (square-wave input) dbm -15 >-25 +10 @ | in = 500 mhz, (sine-wave input) dbm -15 >-20 +10 p in | in = 1 to 8 ghz dbm -15 >-20 +10 | in = 8 to 10 ghz dbm -10 >-15 +5 | in = 10 to 12 ghz dbm -5 >-10 -1 rl small-signal input/output return loss (@ | in < 12 ghz) db 15 s 12 small-signal reverse isolation (@ | in < 10 ghz) db 30 j n ssb phase noise (@ p in = 0 dbm, 100 khz offset dbc/hz -153 from a | out = 1.2 ghz carrier jitter input signal time variation @ zero-crossing ps 1 ( | in = 10 ghz, p in = -10 dbm) t r or t f output edge speed (10% to 90% rise/fall time) ps 70 notes: 1. for sine-wave input signal. prescaler will operate down to d.c. for square-wave input signal. minimum divide frequency limited by input slew-rate. 2. prescaler may exhibit this output signal under bias in the absence of an rf input signal. this condition may be elimi- nated by use of the pre-amp disable (v disable ) or prescaler power-down (v pwrdwn ) features, or the differential input de-biasing technique. v rfout (q)
3 HMMC-3028 rf specifications, high output power operating mode [1] (t a = 25 c, z o = 50 w , v cc - v ee = 5.0 v) symbol parameters and test conditions units min. typ. max. @ | out < 1 ghz dbm -2.0 0 p out @ | out = 1.25 ghz dbm -2.0 0 @ | out = 1.5 ghz dbm -2.25 -0.25 @ | out < 1 ghz volts 0.39 0.5 |v out(p-p) |@ | out = 1.25 ghz volts 0.39 0.5 @ | out = 1.5 ghz volts 0.38 0.48 | out power level appearing at rfin or rfin p spitback (@ | in = 10 ghz, unused rfout or rfout unterminated ) dbm -61 | out power level appearing at rfin or rfin (@ | in = 10 ghz, both rfout & rfout terminated ) dbm -81 p feedthru power level of | in appearing at rfout or rfout (@ | in = 10 ghz, p in = 0 dbm, referred to p in ( | in )) dbc -30 h 2 second harmonic distortion output level (@ | out = 1.5 ghz, referred to p out ( | out )) dbc -30 low output power operating mode [2] symbol parameters and test conditions units min. typ. max. @ | out < 1 ghz dbm -7.5 -5.5 p out @ | out = 1.25 ghz dbm -7.5 -5.5 @ | out = 1.5 ghz dbm -7.75 -5.75 @ | out < 1 ghz volts 0.21 0.26 |v out(p-p) |@ | out = 1.25 ghz volts 0.21 0.26 @ | out = 1.5 ghz volts 0.20 0.26 | out power level appearing at rfin or rfin p spitback (@ | in = 10 ghz, unused rfout or rfout unterminated ) dbm -71 | out power level appearing at rfin or rfin (@ | in = 10 ghz, both rfout & rfout terminated ) dbm -91 p feedthru power level of | in appearing at rfout or rfout (@ | in = 12 ghz, p in = 0 dbm, referred to p in ( | in )) dbc -30 h 2 second harmonic distortion output level (@ | out = 1.5 ghz, referred to p out ( | out )) dbc -35 notes: 1. v pwrsel = v ee . 2. v pwrsel = open circuit. figure 1. HMMC-3028 simplified schematic. v cc input preamplifier stage rf in 50 50 rf in v ee v cc v ee v pwrsel 18/36 ma v pwrdwn post amplifier stage 50 50 rfout rfout v disable divide cell 8
4 applications the HMMC-3028 is designed for use in high frequency communi- cations, microwave instrumenta- tion and ew radar systems where low phase-noise pll control circuitry or broad-band frequency translation is required. operation the device is designed to operate when driven with either a single- ended or differential sinusoidal input signal over a 200 mhz to 12 ghz bandwidth. below 200 mhz the prescaler input is slew-rate limited requiring fast rising and falling edge speeds to properly divide. the device will operate at frequencies down to dc when driven with a square- wave. ac coupling at the rfin pad is recommended for most applications. the device can be operated from either a single positive or single negative supply. for positive supply operation v cc is nominally biased at any voltage in the +4.5 to +6.5 volt range with v ee (or v ee & v pwrsel ) grounded. for negative bias operation v cc is typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to v ee (or v ee & v pwrsel ). several features are designed into this prescaler: 1) dual-output power feature bonding both v ee and v pwrsel pads to either ground (positive bias mode) or the negative supply (negative bias mode), will deliver ~0 dbm [0.5 v p-p ] at the rf output port while drawing ~44 ma supply current. eliminating the v pwrsel connection results in reduced output power and voltage swing, -6.0 dbm [0.25 v p-p ] but at a reduced current draw of ~34 ma resulting in less overall power dissipation. (note: v ee must always be bonded and v pwrsel must never be biased to any potential other than v ee or open-circuited.) 2) v logic ecl contact pad under normal conditions no connection or external bias is required to this pad and it is self- biased to the on-chip ecl logic threshold voltage (v cc -1.35 v). the user can provide an external bias to this pad (1.5 to 1.2 volts less than v cc ) to force the prescaler to operate at a system generated logic threshold voltage. 3) input disable feature by applying an external bias to this contact pad (more positive than v cc - 1.35 v), the input preamplifier stage is locked into either logic high or logic low preventing frequency division and any self-oscillation frequency which may be present. 4) prescaler power-down by applying an external bias to this contact pad (more positive than v ee + 3.2 v), the supply current can be reduced to ~5 ma also preventing frequency divi- sion and any self-oscillation fre- quency which may be present while decreasing the power dissipation to ~zero. 5) input dc offset another method used to prevent false triggers or self-oscillation conditions is to apply a 20 to 100 mv dc offset voltage be- tween the rfin and rfin ports. this prevents noise or spurious low level signals from triggering the divider. optional dc operating values / logic levels (t a = 25 c) function symbol conditions min. typical max. (volts/ma) (volts/ma) (volts/ma) logic threshold [1] v logic v cc - 1.5 v cc - 1.35 v cc - 1.2 v disable(high) [disable] v logic + 0.25 v logic v cc input disable v disable(low) [enable] v ee v logic - 0.25 i disable v d > v ee + 3 (v disable - v ee - 3) / 500 v d < v ee + 3 0 v pwrdwn(high) [power-down] v ee + 3.9 v ee + 3.2 v cc prescaler v pwrdwn(low) [power-up] v ee v ee + 2.7 power-down i pwrdwn v p > v ee + 2.7 (v pwrdwn -v ee - 3) / 500 v p < v ee + 2.7 0 note: 1. acceptable voltage range when applied from external source.
5 assembly techniques figure 3 shows the chip assem- bly diagram for single-ended i/o operation through 12 ghz. for positive supply operation, v cc is typically biased to a pos- itive voltage between +4.5 and +6.5 volts and v ee is grounded. for negative supply operation, v ee is typically biased between -4.5 to -6.5 volts and v cc is grounded. in either case the supply contact to the chip must be capacitively bypassed to pro- vide good input sensitivity and low input power feedthrough. all bonds between the device and this bypass capacitor should be as short as possible to limit the inductance. for operation at frequencies below 1 ghz, a large value capacitor must be added to provide proper rf bypassing. to aid in providing higher fre- quency bypassing a special v cc(bypass) pad has been added to the chip and must be tied to rf ground. in general, ac coupling capaci- tors are recommended on the rfin and rfout connections to the device. for negative supply operation the ac coupling cap is not critical since v cc is typi- cally grounded and the dc volt- age present on rfin/rfout is ~0 volts. for positive supply operation, v cc is positively biased resulting in a positive dc voltage appearing at rfin or rfout. in this case a ac coupling cap is required. due to on-chip 50 w matching resistors at all four rf ports, no external termination is required. however, improved spitback performance (~ 20 db) and input sensitivity can be achieved by terminating the unused rfout port to v cc through 50 w (positive supply) or to ground via a 50 w termination (negative supply operation). for proper handling, die-attach and electrical interconnection techniques of esd sensitive components see agilent application note #999, gaas mmic assembly and handling guidelines. gaas mmics are esd sensitive. proper precautions should be used when handling these devices. figure 2. HMMC-3028 pad locations and chip dimensions. 0 440 0 rfin 220 70 370 70 650 800 950 1090 1260 350 230 900 260 500 1330 rfin v cc v ccbypass v pwrdwn v pwrsel v logic v disable v ee v cc v cc rfout rfout v cc notes: ? all dimensions in microns. ? all pad dim: 70 x 70 m (except where noted) ? tolerances: 10 m ? chip thickness: 127 15 m
6 figure 3. HMMC-3028 assembly diagrams. to +4.5v to +6.5v v cc supply (bypassed via 1 f capacitor) >300 pf v cc bypass capacitor v ee bond required (gnd) positive supply 3 mil nominal gap (@ device input) ac coupling capacitor(s) ac coupling capacitor (note: must be large enough to pass lowest frequency output signal) rfin rfout rfout rfin optional differential output optional differential input optional 50 termination to v cc or gnd if ac coupling cap is employe d optional v pwrsel pad connection: w/pad bonded to ground: high p out assembly (0 dbm [0.5 v p-p ] @ i cc = 44 ma) w/pad not bonded to ground: low p out assembly (-6.0 dbm [0.25 v p-p ] @ i cc = 34 ma) to -4.5v to -6.5v v ee supply (bypassed via 1 f capacitor) >300 pf v ee bypass capacitor v ee bond required negative supply 3 mil nominal gap (@ device input) rfin rfout rfout rfin optional differential output optional differential input optional 50 termination optional v pwrsel pad connection: w/pad bonded to v ee : high p out assembly (0 dbm [0.5 v p-p ] @ i cc = 44 ma) w/pad not bonded to v ee : low p out assembly (-6.0 dbm [0.25 v p-p ] @ i cc = 34 ma) v cc (bypass) connection to rf ground-plane required)
7 HMMC-3028 supplemental data 0 2 4 input frequency, in (ghz) v cc ? ee = +5 v, t a = 25 c 20 10 0 -10 -20 -30 -40 input power, p in (dbm) 12 8 610 16 14 50 45 40 35 30 25 20 15 10 5 0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 i supply (ma) v logic ?v cc (v) 01 2 5 34 78 69 v cc ? ee (v) t a = 25 c high power mode low power mode figure 6. typical hmmc-3022/3024/3028 phase noise performance. 2 0 -2 -4 -6 p out (@ p in = 0 dbm) (dbm) 0 0.5 1 2.5 1.5 2 output frequency (ghz) high power mode low power mode v cc ? ee = +5 v, t a = 25 c 024 input frequency, in (ghz) v cc ? ee = +5 v, p in = 0 dbm, t a = 25 c -50 -60 -70 -80 -90 -100 -110 -120 p spitback (dbm) 12 8 610 16182022 14 unterminated rfout port both rfout ports terminated figure 4. typical hmmc-3022/3024/3028 input sensitivity window. figure 5. typical supply current & v logic vs. supply voltage. figure 7. typical output power vs. output frequency, ? out (ghz). figure 8. typical hmmc-3022/3024/3028 spitback power. p(? out ) appearing at rf input port. -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 100 1k 10k 100k 1m 10m x [ f ] [dbc/hz vs. f [hz ] hbt divide by 4 residual noise hp 3048a carrier: 12e9 hz 6/11/95 17:12:42 ?17:19:23
this data sheet contains a variety of typical performance data. the information supplied should not be interpreted as a complete list of circuit specifications. in this data sheet the term typical refers to the 50th percentile performance. for additional information contact your local agilent sales representative. figure 9. hmmc-3128 package and dimensions. (available in near future.) figure 10. hmmc-3128 assembly diagram. (single-supply, positive-bias configuration shown) v ee pin 1 v cc v cc v cc rfin rfin 3.80/4.00 5.80/6.20 4.80/5.00 rfout rfout 1.35/1.75 0 /8 0.10/0.25 0.19/.025 pin 8 0.33/0.51 0.40/1.27 1.27 bsc notes: all dimensions are min./max. in millimeters. refer to jedec outline mo-150 for additional tolerances. v ee v cc rfin rfin v cc v cc rfout rfout v cc (+4.5 to +6.5 volts) ~1 f monoblock capacitor to operate component from a negative supply, ground each v cc connection and supply v ee with a negative voltage (-4.5 to -6.5 v) bypassed to ground with ~1 f capacitor. rfout should be terminated in 50 to ground (dc blocking capacitor required for positive bias configuration.) www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies obsoletes 5968-1781e 5968-4527e (11/99)
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